TITLE: New Algorithms and Architectures for Post-Silicon Validation (2009)
BibTeX
@MISC{Ko09title:new,
author = {Fai Ko and B. Eng and M. A. Sc. (electrical},
title = {TITLE: New Algorithms and Architectures for Post-Silicon Validation},
year = {2009}
}
Share
 |
 |
 |
 |
||
OpenURL
Abstract
To identify design errors that escape pre-silicon verification, post-silicon validation is becoming an important step in the implementation flow of digital integrated circuits. While many debug problems are tackled on testers, there are hard-to-find design errors that are activated only in-system. A key challenge during in-system debugging is to acquire data from internal circuit’s nodes in real-time. In this thesis, we propose several techniques to address this problem, ranging from resource-efficient and programmable trigger units to automated selection of trace signals to a distributed architecture for embedded logic analysis. Deciding when to acquire data on-chip is done using trigger units. Because there is an inherent tradeoff between the size of the trigger units and the types of events that can be programmed into them, we first explore a resource-efficient and programmable trigger unit implementation. We show how the on-chip buffers used for data acquisition can be leveraged to store information regarding the logic functions that are programmed at runtime as the trigger events. This reduces the requirement in terms
Keyphrases
post-silicon validation new algorithm trigger unit trace signal data on-chip pre-silicon verification data acquisition programmable trigger unit implementation digital integrated circuit logic function design error distributed architecture trigger event in-system debugging inherent tradeoff on-chip buffer automated selection key challenge implementation flow important step many debug problem several technique internal circuit node programmable trigger unit hard-to-find design error embedded logic analysis
