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Tolerating Memory Latency through Software-Controlled Pre-Execution in Simultaneous Multithreading Processors (2001)
| Venue: | In Proceedings of the 28th Annual International Symposium on Computer Architecture |
| Citations: | 174 - 0 self |
BibTeX
@INPROCEEDINGS{Luk01toleratingmemory,
author = {Chi-Keung Luk},
title = {Tolerating Memory Latency through Software-Controlled Pre-Execution in Simultaneous Multithreading Processors},
booktitle = {In Proceedings of the 28th Annual International Symposium on Computer Architecture},
year = {2001},
pages = {40--51}
}
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Abstract
Hardly predictable data addresses in many irregular applications have rendered prefetching ineffective. In many cases, the only accurate way to predict these addresses is to directly execute the code that generates them. As multithreaded architectures become increasingly popular, one attractive approach is to use idle threads on these machines to perform pre-execution---essentially a combined act of speculative address generation and prefetching--- to accelerate the main thread. In this paper, we propose such a pre-execution technique for simultaneous multithreading (SMT) processors. By using software to control pre-execution, we are able to handle some of the most important access patterns that are typically difficult to prefetch. Compared with existing work on pre-execution, our technique is significantly simpler to implement (e.g., no integration of pre-execution results, no need of shortening programs for pre-execution, and no need of special hardware to copy register values upon thread spawns). Consequently, only minimal extensions to SMT machines are required to support our technique. Despite its simplicity, our technique offers an average speedup of 24% in a set of irregular applications, which is a 19% speedup over state-of-the-art software-controlled prefetching.
Keyphrases
software-controlled pre-execution simultaneous multithreading processor memory latency thread spawn combined act minimal extension many case main thread attractive approach predictable data address pre-execution technique average speedup simultaneous multithreading smt machine pre-execution result speculative address generation state-of-the-art software-controlled prefetching register value many irregular application idle thread irregular application special hardware important access pattern accurate way
