Formal Property Verification by Abstraction Refinement with Formal, Simulation and Hybrid Engines (2001)
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| Venue: | In Proceedings of the DAC |
| Citations: | 33 - 4 self |
BibTeX
@INPROCEEDINGS{Wang01formalproperty,
author = {Dong Wang and Pei-Hsin Ho and Jiang Long and James Kukula and Yunshan Zhu and Tony Ma and Robert Damiano},
title = {Formal Property Verification by Abstraction Refinement with Formal, Simulation and Hybrid Engines},
booktitle = {In Proceedings of the DAC},
year = {2001},
pages = {35--40}
}
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Abstract
and BDD-based symbolic image computation to find an error trace on the subcircuit. RFN also computes a forward fixpoint using post-image computation to verify the unreachability property on the subcircuit. If the property is True for the subcircuit, RFN reports that the property is True for the original design and terminates. Otherwise it proceeds to Step 3. In Step 3 we want to find error traces on real-world designs. RFN utilizes the error trace found on the subcircuit to guide sequential ATPG to search for an error trace on the original design. If an error trace of the original design is found, RFN reports that the property is False, prints out the error trace and terminates. Otherwise RFN proceeds to Step 4. In Step 4 we select a set E of registers that are in the original model but not in the abstract model to refine the abstract model. The refined abstract model will be the current abstract model augmented with the set E of registers plus their transitive fanins up to register ...
