Static Energy Reduction Techniques for Microprocessor Caches (2001)
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| Venue: | In 2001 International Conference on Computer Design |
| Citations: | 51 - 5 self |
BibTeX
@INPROCEEDINGS{Hanson01staticenergy,
author = {Heather Hanson and M.S. Hrishikesh and Vikas Agarwal and Stephen W. Keckler and Doug Burger},
title = {Static Energy Reduction Techniques for Microprocessor Caches},
booktitle = {In 2001 International Conference on Computer Design},
year = {2001},
pages = {276--283}
}
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Abstract
Microprocessor performance has been improved by increasing the capacity of on-chip caches. However, the performance gain comes at the price of increased static energy consumption due to subthreshold leakage current. This paper compares three techniques for reducing static energy consumption in on-chip level-1 and level-2 caches. One technique employs low-leakage transistors in the memory cell. Another technique, power supply switching, can be used to turn off memory cells and discard their contents. A third alternative is dynamic threshold modulation, which places memory cells in a standby state that preserves cell contents. In our experiments, we explore the energy/performance trade-offs of these techniques and find that dynamic threshold modulation achieves the best results for level-1 caches, improving the energy-delay product by 2% in a level-1 instruction cache and 7% in a level-1 data cache. Low-leakage transistors perform best for the level-2 cache as they reduce static energy by up to 98% and improve the energy-delay product by more than a factor of 50. 1
Keyphrases
memory cell microprocessor cache static energy reduction technique energy-delay product low-leakage transistor dynamic threshold modulation level-2 cache microprocessor performance cell content static energy consumption level-1 instruction cache power supply on-chip cache level-1 cache increased static energy consumption standby state performance gain level-1 data cache third alternative energy performance trade-off static energy
