The Stanford FLASH multiprocessor

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The Stanford FLASH multiprocessor (1994)

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by Jeffrey Kuskin , David Ofelt , Mark Heinrich , John Heinlein , Richard Simoni , Kourosh Gharachorloo , John Chapin , David Nakahira , Joel Baxter , Mark Horowitz , Anoop Gupta , Mendel Rosenblum , John Hennessy

Venue:	In Proceedings of the 21st International Symposium on Computer Architecture
Citations:	349 - 20 self

BibTeX

@INPROCEEDINGS{Kuskin94thestanford,
    author = {Jeffrey Kuskin and David Ofelt and Mark Heinrich and John Heinlein and Richard Simoni and Kourosh Gharachorloo and John Chapin and David Nakahira and Joel Baxter and Mark Horowitz and Anoop Gupta and Mendel Rosenblum and John Hennessy},
    title = {The Stanford FLASH multiprocessor},
    booktitle = {In Proceedings of the 21st International Symposium on Computer Architecture},
    year = {1994},
    pages = {302--313}
}

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Abstract

The FLASH multiprocessor efficiently integrates support for cache-coherent shared memory and high-performance message passing, while minimizing both hardware and software overhead. Each node in FLASH contains a microprocessor, a portion of the machine’s global memory, a port to the interconnection network, an I/O interface, and a custom node controller called MAGIC. The MAGIC chip handles all communication both within the node and among nodes, using hardwired data paths for efficient data movement and a programmable processor optimized for executing protocol operations. The use of the protocol processor makes FLASH very flexible — it can support a variety of different communication mechanisms — and simplifies the design and implementation. This paper presents the architecture of FLASH and MAGIC, and discusses the base cache-coherence and message-passing protocols. Latency and occupancy numbers, which are derived from our system-level simulator and our Verilog code, are given for several common protocol operations. The paper also describes our software strategy and FLASH’s current status. 1

Keyphrases

stanford flash multiprocessor software strategy verilog code several common protocol operation machine global memory programmable processor protocol processor custom node controller base cache-coherence current status efficient data movement data path cache-coherent shared memory occupancy number high-performance message passing flash multiprocessor interconnection network message-passing protocol different communication mechanism system-level simulator software overhead protocol operation magic chip

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