Reducing DRAM latencies with an integrated memory hierarchy design

Reducing DRAM latencies with an integrated memory hierarchy design (2001)

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by Wei-fen Lin , Steven K. Reinhardt , Doug Burger

Venue:	In Proceedings of the 7th International Symposium on High Performance Computer Architecture (HPCA-7
Citations:	109 - 7 self

BibTeX

@INPROCEEDINGS{Lin01reducingdram,
    author = {Wei-fen Lin and Steven K. Reinhardt and Doug Burger},
    title = {Reducing DRAM latencies with an integrated memory hierarchy design},
    booktitle = {In Proceedings of the 7th International Symposium on High Performance Computer Architecture (HPCA-7},
    year = {2001}
}

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Abstract

In this papel; we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory system using four Direct Rambus channels and an integrated one-megabyte level-two cache, a processor still spends over half of its time stalling for L2 misses. Large cache blocks can improve performance, but only when coupled with wide memory channels. DRAM address mappings also affect performance significantly. We evaluate an aggressive prefetch unit integrated with the L2 cache and memory controllers. By issuing prefetches only when the Rambus channels are idle, prioritizing them to maximize DRAM row bufSer hits, and giving them low replacement priority, we achieve a 43% speedup across IO of the 26 SPEC2000 benchmarks, without degrading performance on the others. With eight Rambus channels, these ten benchmarks improve to within 10 % of the peflormance of a perfect L2 cache. 1.

Keyphrases

integrated memory hierarchy design dram latency rambus channel integrated one-megabyte level-two cache next-generation memory system aggressive prefetch unit high processor clock rate bufser hit perfect l2 cache severe performance gap ten benchmark dram address mapping wide memory channel l2 miss low replacement priority dram access memory controller l2 cache large cache block spec2000 benchmark direct rambus channel