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Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures (2000)
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BibTeX
@MISC{Agarwal00clockrate,
author = {Vikas Agarwal and M.S. Hrishikesh and Stephen W. Keckler and Doug Burger},
title = {Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures},
year = {2000}
}
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Abstract
The doubling of microprocessor performance every three years has been the result of two factors: more transistors per chip and superlinear scaling of the processor clock with technology generation. Our results show that, due to both diminishing improvements in clock rates and poor wire scaling as semiconductor devices shrink, the achievable performance growth of conventional microarchitectures will slow substantially. In this paper, we describe technology-driven models for wire capacitance, wire delay, and microarchitectural component delay. Using the results of these models, we measure the simulated performance---estimating both clock rate and IPC--- of an aggressive out-of-order microarchitecture as it is scaled from a 250nm technology to a 35nm technology. We perform this analysis for three clock scaling targets and two microarchitecture scaling strategies: pipeline scaling and capacity scaling. We find that no scaling strategy permits annual performance improvements of better than 12.5%, which is far worse than the annual 50-60% to which we have grown accustomed. 1
Keyphrases
conventional microarchitectures clock rate versus ipc clock rate microprocessor performance wire delay superlinear scaling semiconductor device processor clock achievable performance growth scaling strategy microarchitectural component delay capacity scaling technology generation simulated performance annual performance improvement aggressive out-of-order microarchitecture pipeline scaling wire capacitance poor wire scaling technology-driven model annual 50-60
