DMCA
Static Partitioning vs Dynamic Sharing of Resources in Simultaneous MultiThreading Microarchitectures
BibTeX
@MISC{Liu_staticpartitioning,
author = {Chen Liu and Jean-luc Gaudiot},
title = {Static Partitioning vs Dynamic Sharing of Resources in Simultaneous MultiThreading Microarchitectures},
year = {}
}
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Abstract
Abstract. Simultaneous MultiThreading (SMT) achieves better system resource utilization and higher performance because it exploits Thread-Level Parallelism (TLP) in addition to “conventional ” Instruction-Level Parallelism (ILP). Theoretically, system resources in every pipeline stage of an SMT microarchitecture can be dynamically shared. However, in commercial applications, all the major queues are statically partitioned. From an implementation point of view, static partitioning of resources is easier to implement and has a lower hardware overhead and power consumption. In this paper, we strive to quantitatively determine the tradeoff between static partitioning and dynamic sharing. We find that static partitioning of either the instruction fetch queue (IFQ) or the reorder buffer (ROB) is not sufficient if implemented alone (3 % and 9 % performance decrease respectively in the worst case comparing with dynamic sharing), while statically partitioning both the IFQ and the ROB could achieve an average performance gain of 9 % at least, and even reach 148% when running with floating-point benchmarks, when compared with dynamic sharing. We varied the number of functional units in our efforts to isolate the reason for this performance improvement. We found that static partitioning both queues outperformed all the other partitioning mechanisms under the same system configuration. This demonstrates that the performance gain has been achieved by moving from dynamic sharing to static partitioning of the system resources. 1
Keyphrases
static partitioning static partitioning v dynamic sharing simultaneous multithreading microarchitectures system resource average performance gain thread-level parallelism smt microarchitecture reorder buffer major queue performance decrease system configuration pipeline stage conventional instruction-level parallelism floating-point benchmark hardware overhead instruction fetch queue implementation point simultaneous multithreading system resource utilization power consumption performance gain performance improvement dynamic sharing functional unit commercial application
