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Locality vs. Criticality (2001)
| Citations: | 49 - 0 self |
BibTeX
@MISC{Srinivasan01localityvs.,
author = {Srikanth T. Srinivasan and Roy Dz-ching Ju and Alvin R. Lebeck and Chris Wilkerson},
title = {Locality vs. Criticality},
year = {2001}
}
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Abstract
Current memory hierarchies exploit locality of references to reduce load latency and thereby improve processor performance. Locality based schemes aim at reducing the number of cache misses and tend to ignore the nature of misses. This leads to a potential mis-match between load latency requirements and latencies realized using a traditional memory system. To bridge this gap, we partition loads as critical and non-critical. A load that needs to complete early to prevent processor stalls is classified as critical, while a load that can tolerate a long latency is considered non-critical. In this paper, we investigate if it is worth violating locality to exploit information on criticality to improve processor performance. We present a dynamic critical load classification scheme and show that 40% performance improvements are possible on average, if all critical loads are guaranteed to hit in the L1 cache. We then compare the two properties, locality and criticality, in the context of several cache organization and prefetching schemes. We find that the working set of critical loads is large, and hence practical cache organization schemes based on criticality are unable to reduce the critical load miss ratios enough to produce performance gains. Although criticality-based prefetching can help for some resource constrained programs, its benefit over locality-based prefetching is small and may not be worth the added complexity.
Keyphrases
locality v critical load processor performance cache miss critical load miss ratio load latency load latency requirement dynamic critical load classification scheme locality-based prefetching l1 cache several cache organization potential mis-match current memory hierarchy added complexity long latency criticality-based prefetching traditional memory system performance gain performance improvement practical cache organization scheme processor stall
