Compiler-Directed Dynamic Voltage Scaling for Memory-Bound Applications (2002)
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BibTeX
@MISC{Hsu02compiler-directeddynamic,
author = {Chung-hsing Hsu and Ulrich Kremer},
title = {Compiler-Directed Dynamic Voltage Scaling for Memory-Bound Applications},
year = {2002}
}
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Abstract
This paper presents the design and implementation of a compiler algorithm that effectively reduces the energy usage of memory-bound applications via dynamic voltage scaling (DVS). The algorithm identifies program regions where the CPU can be slowed down with negligible performance penalty. It is implemented as a source-to-source level transformation using the SUIF2 compiler infrastructure. Physical measurements on a laptop with a 600 MHz - 1.2 GHz AMD Athlon 4 processor show that CPU energy savings in the range of 9.17% to 55.65% can be achieved with performance degradation in the range of 0.69% to 6.14% for the SPECfp95 benchmarks. On average, the energy and energy-delay product are reduced by 26.58% and 24.11%, respectively, at the cost of the performance slowdown of 3.26%. This paper also discusses a new methodology which attempts to approximate the minimum energy usage by any DVS algorithm. Our compiler-directed DVS algorithm is within 6% from the "optimal" case. To the best of our knowledge, this is one of the first work that evaluates DVS strategies by physical measurements.
