DMCA
A Tightly-Coupled Processor-Network Interface (1992)
| Venue: | IN PROCEEDINGS OF THE FIFTH INTERNATIONAL CONFERENCE ON ARCHITECTURAL SUPPORT FOR PROGRAMMING LANGUAGES AND OPERATING SYSTEMS (ASPLOS V |
| Citations: | 85 - 3 self |
BibTeX
@INPROCEEDINGS{Joerg92atightly-coupled,
author = {Christopher F. Joerg and Dana S Henry},
title = {A Tightly-Coupled Processor-Network Interface},
booktitle = {IN PROCEEDINGS OF THE FIFTH INTERNATIONAL CONFERENCE ON ARCHITECTURAL SUPPORT FOR PROGRAMMING LANGUAGES AND OPERATING SYSTEMS (ASPLOS V},
year = {1992},
pages = {111--122},
publisher = {}
}
Share
 |
 |
 |
 |
||
OpenURL
Abstract
Careful design of the processor-network interface can dramatically reduce the software overhead of interprocessor communication. Our interface architecture reduces communication overhead five fold in our benchmarks. Most of our performance gain comes from simple, low cost hardware mechanisms for fast dispatching on, forwarding of, and replying to messages. The remaining improvement can be gained by implementing the network interface as part of the processor's register file. For example, using our hardware mechanisms a register-mapped interface can receive, process, and reply to a remote read request in a total of two RISC instructions. We have implemented an RTL model of an off-chip memory-mapped interface which provides our hardware mechanisms. Our industrial partner, Motorola, is implementing a similar network interface on-chip in an experimental version of the 88110 processor.
Keyphrases
tightly-coupled processor-network interface off-chip memory-mapped interface interprocessor communication risc instruction fast net hardware mechanism experimental version processor-network interface rtl model fast parallel computer fast processor industrial partner register file network interface low cost hardware mechanism performance gain interface architecture remote read request careful design register-mapped interface similar network interface on-chip software overhead
