DMCA
Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies
BibTeX
@MISC{Huang_modelingthe,
author = {Zhangcai Huang and Atsushi Kurokawa and Masanori Hashimoto and Takashi Sato and Minglu Jiang and Yasuaki Inoue},
title = {Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies},
year = {}
}
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Abstract
Abstract—With the scaling of complementary metal–oxide– semiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacitance has more significant influence on CMOS gate analysis, especially on CMOS gate static timing analysis. In this paper, the overshooting effect is modeled for CMOS inverter delay analysis in nanometer technologies. The results produced by the proposed model are close to simulation program with integrated circuit emphasis (SPICE). Moreover, the influence of the overshooting effect on CMOS inverter analysis is discussed. An analytical model is presented to calculate the CMOS inverter delay time based on the proposed overshooting effect model, which is verified to be in good agreement with SPICE results. Furthermore, the proposed model is used to improve the accuracy of the switch-resistor model for approximating the inverter output waveform. Index Terms—CMOS inverter, gate delay, nanometer technology, overshooting time, switch-resistor model, timing analysis. I.
Keyphrases
nanometer technology cmos inverter delay analysis overshooting effect switch-resistor model inverter output waveform gate delay simulation program nanometer regime complementary metal cmos gate analysis overshooting effect model integrated circuit emphasis index term cmos inverter good agreement cmos inverter analysis significant influence cmos inverter delay time input-to-output coupling capacitance analytical model spice result cmos gate static timing analysis
