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Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors (1990)
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| Venue: | In Proceedings of the 17th Annual International Symposium on Computer Architecture |
| Citations: | 730 - 17 self |
BibTeX
@INPROCEEDINGS{Gharachorloo90memoryconsistency,
author = {Kourosh Gharachorloo and Daniel Lenoski and James Laudon and Phillip Gibbons and Anoop Gupta and John Hennessy},
title = {Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors},
booktitle = {In Proceedings of the 17th Annual International Symposium on Computer Architecture},
year = {1990},
pages = {15--26}
}
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Abstract
Scalable shared-memory multiprocessors distribute memory among the processors and use scalable interconnection networks to provide high bandwidth and low latency communication. In addition, memory accesses are cached, buffered, and pipelined to bridge the gap between the slow shared memory and the fast processors. Unless carefully controlled, such architectural optimizations can cause memory accesses to be executed in an order different from what the programmer expects. The set of allowable memory access orderings forms the memory consistency model or event ordering model for an architecture.
Keyphrases
scalable shared-memory multiprocessor event ordering memory consistency memory access allowable memory access ordering use scalable interconnection network low latency communication fast processor scalable shared-memory multiprocessor distribute memory high bandwidth memory consistency model architectural optimization
