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The MPC Parallel Computer: Hardware, Low-level Protocols and Performances (2000)
| Venue: | in Proc of IASTED Parallel and Distributed Computing and Systems (PDCS 2000), Las Vegas |
| Citations: | 1 - 1 self |
BibTeX
@INPROCEEDINGS{Zerrouki00thempc,
author = {Amal Zerrouki and Olivier Glück and O. Gluck and Jean-Lou Desbarbieux and Alexandre Fenyö and Alain Greiner and Cyril Spasevski and Fabricio Silva and Emmanuel Dreyfus and Frank Wajsbürt and Silva E. Dreyfus},
title = {The MPC Parallel Computer: Hardware, Low-level Protocols and Performances},
booktitle = {in Proc of IASTED Parallel and Distributed Computing and Systems (PDCS 2000), Las Vegas},
year = {2000},
pages = {87--92}
}
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Abstract
This paper presents the MPC parallel computer and its MPI implementation performed at the Laboratoire LIP6 of Univ. Pierre and Marie Curie, Paris. MPC is a low cost and high performance parallel computer using standard PC motherboards as processing nodes connected through the specific FastHSL board to a high speed communication network using HSL 1 Gbits/s serial links, IEEE 1355 compliant. Two Asics are presented : RCUBE which is the HSL network router, and PCI-DDC the network controller implementing the Direct Deposit State Less receiver protocol.
