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Exploring Speculative Parallelism in SPEC2006
BibTeX
@MISC{Packirisamy_exploringspeculative,
author = {Venkatesan Packirisamy and Antonia Zhai and Wei-chung Hsu and Pen-chung Yew and Tin-fook Ngai},
title = {Exploring Speculative Parallelism in SPEC2006},
year = {}
}
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Abstract
The computer industry has adopted multi-threaded and multicore architectures as the clock rate increase stalled in early 2000’s. It was hoped that the continuous improvement of single-program performance could be achieved through these architectures. However, traditional parallelizing compilers often fail to effectively parallelize general-purpose applications which typically have complex control flow and excessive pointer usage. Recently hardware techniques such as Transactional Memory (TM) and Thread-Level Speculation (TLS) have been proposed to simplify the task of parallelization by using speculative threads. Potential of speculative parallelism in general-purpose applications like SPEC CPU 2000 have been well studied and shown to be moderately successful. Preliminary work examining the potential parallelism in SPEC2006 deployed parallel threads with a restrictive TLS execution model and limited compiler support, and thus only showed limited performance potential. In this paper, we first analyze the cross-iteration dependence behavior of SPEC 2006 benchmarks and show that more parallelism potential is available in SPEC 2006 benchmarks, comparing to SPEC2000. We further use a state-of-the-art profile-driven TLS compiler to identify loops that can be speculatively parallelized. Overall, we found that with optimal loop selection we can potentially achieve an average speedup of 60 % on four cores over what could be achieved by a traditional parallelizing compiler such as Intel’s ICC compiler. We also found that an additional 11 % improvement can be potentially obtained on selected benchmarks using 8 cores when we extend TLS on multiple loop levels as opposed to restricting to a single loop level. I.
Keyphrases
speculative parallelism traditional parallelizing compiler general-purpose application excessive pointer usage limited performance potential parallel thread transactional memory parallelism potential restrictive tl execution model computer industry potential parallelism multicore architecture limited compiler support complex control flow continuous improvement speculative thread average speedup single-program performance state-of-the-art profile-driven tl compiler clock rate increase icc compiler multiple loop level preliminary work spec cpu optimal loop selection cross-iteration dependence behavior thread-level speculation hardware technique single loop level
