Scalable Caching Techniques for a Weakly Coherent Memory (1995)
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BibTeX
@MISC{Zamanifar95scalablecaching,
author = {K. Zamanifar and J. M. Nash and P.M. Dew},
title = {Scalable Caching Techniques for a Weakly Coherent Memory},
year = {1995}
}
OpenURL
Abstract
Machines Workshop'96 Abstract There is a growing acceptance that general purpose parallel computers need to be based on a scalable shared memory computational model, with the ability to exploit data locality for good performance. Today, this is commonly achieved by mapping the model onto a distributed memory computer with a scalable interconnect (supporting linear increases in bisection bandwidth). Example machines are the Cray T3D, IBM SP2 and Intel Paragon, which can scale in performance to 100's or 1000's of processors. This results in a two-level memory hierarchy, in which data is either local or shared across the machine. The next few years will see a trend in the move towards cache coherent multiprocessors, using the techniques employed by machines such as the KSR (cache-only memory) and the DASH (distributed directories). An example is the forthcoming Silicon Graphics cache coherent multiprocessor. This will simplify the programming model by presenting a single level memory h...







