Scalable high performance main memory system using phase-change memory technology (2009)
| Venue: | In International Symposium on Computer Architecture (ISCA |
| Citations: | 34 - 1 self |
BibTeX
@INPROCEEDINGS{Qureshi09scalablehigh,
author = {Moinuddin K. Qureshi and Vijayalakshmi Srinivasan and Jude A. Rivers},
title = {Scalable high performance main memory system using phase-change memory technology},
booktitle = {In International Symposium on Computer Architecture (ISCA},
year = {2009}
}
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Abstract
The memory subsystem accounts for a significant cost and power budget of a computer system. Current DRAM-based main memory systems are starting to hit the power and cost limit. An alternative memory technology that uses resistance contrast in phase-change materials is being actively investigated in the circuits community. PhaseChangeMemory(PCM) devices offer more density relative to DRAM, and can help increase main memory capacity of future systems while remaining within the cost and power constraints. In this paper, we analyze a PCM-based hybrid main memory system using an architecture level model of PCM. We explore the trade-offs for a main memory system consisting of PCM storage coupled with a small DRAM buffer. Such an architecture has the latency benefits of DRAM and the capacity benefits of PCM. Our evaluations for a baseline system of 16-cores with 8GB DRAM show that, on average, PCM can reduce page faults by 5X and provide a speedup of 3X. As PCM is projected to have limited write endurance, we also propose simple organizational and management solutions of the hybrid memory that reduces the write traffic to PCM, boosting its lifetime from 3 years to 9.7 years. Categories and Subject Descriptors:
