Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power

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Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power (2001)

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by Stefanos Kaxiras , Zhigang Hu , Margaret Martonosi

Venue:	in Proceedings of the 28th International Symposium on Computer Architecture
Citations:	280 - 26 self

BibTeX

@INPROCEEDINGS{Kaxiras01cachedecay:,
    author = {Stefanos Kaxiras and Zhigang Hu and Margaret Martonosi},
    title = {Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power},
    booktitle = {in Proceedings of the 28th International Symposium on Computer Architecture},
    year = {2001},
    pages = {240--251}
}

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Abstract

Power dissipation is increasingly important in CPUs ranging from those intended for mobile use, all the way up to highperformance processors for high-end servers. While the bulk of the power dissipated is dynamic switching power, leakage power is also beginning to be a concern. Chipmakers expect that in future chip generations, leakage’s proportion of total chip power will increase significantly. This paper examines methods for reducing leakage power within the cache memories of the CPU. Because caches comprise much of a CPU chip’s area and transistor counts, they are reasonable targets for attacking leakage. We discuss policies and implementations for reducing cache leakage by invalidating and “turning off ” cache lines when they hold data not likely to be reused. In particular, our approach is targeted at the generational nature of cache line usage. That is, cache lines typically have a flurry of frequent use when first brought into the cache, and then have a period of “dead time ” before they are evicted. By devising effective, low-power ways of deducing dead time, our results show that in many cases we can reduce L1 cache leakage energy by 4x in SPEC2000 applications without impacting performance. Because our decay-based techniques have notions of competitive on-line algorithms at their roots, their energy usage can be theoretically bounded at within a factor of two of the optimal oraclebased policy. We also examine adaptive decay-based policies that make energy-minimizing policy choices on a per-application basis by choosing appropriate decay intervals individually for each cache line. Our proposed adaptive policies effectively reduce L1 cache leakage energy by 5x for the SPEC2000 with only negligible degradations in performance. 1

Keyphrases

exploiting generational behavior cache decay cache line reduce cache leakage power dead time leakage power l1 cache leakage energy reasonable target frequent use cache memory adaptive policy total chip power mobile use future chip generation spec2000 application generational nature many case power dissipation leakage proportion energy usage low-power way competitive on-line algorithm per-application basis cpu chip area appropriate decay interval cache leakage decay-based technique negligible degradation high-end server optimal oraclebased policy adaptive decay-based policy cache line usage transistor count energy-minimizing policy choice

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