Abstract

In this paper, we will introduce two different physical structures and topologies to realize an ethernet layer-2 switch. To evaluate these two structures and produce throughput projections we have utilized MPI. This simulation environment has helped us identify performance bottlenecks and to give an overall estimation of the switch throughput. Our results show that for a hardware implementation of this switch in .18um technology, assuming a 200 MHz clock rate for the processing elements and 100 MHz clock rate for the memory blocks, our design can support multiple gigabit channel ports.

Citations