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Efficient Implementation of Sorting on Multi-Core SIMD CPU Architecture (2008)
| Citations: | 27 - 4 self |
BibTeX
@MISC{Chhugani08efficientimplementation,
author = {Jatin Chhugani and William Macy and Akram Baransi and Anthony D. Nguyen and Mostafa Hagog and Sanjeev Kumar and Victor W. Lee and Yen-kuang Chen and Pradeep Dubey},
title = {Efficient Implementation of Sorting on Multi-Core SIMD CPU Architecture },
year = {2008}
}
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Abstract
Sorting a list of input numbers is one of the most fundamental problems in the field of computer science in general and high-throughput database applications in particular. Although literature abounds with various flavors of sorting algorithms, different architectures call for customized implementations to achieve faster sorting times. This paper presents an efficient implementation and detailed analysis of MergeSort on current CPU architectures. Our SIMD implementation with 128-bit SSE is 3.3X faster than the scalar version. In addition, our algorithm performs an efficient multiway merge, and is not constrained by the memory bandwidth. Our multi-threaded, SIMD implementation sorts 64 million floating point numbers in less than 0.5 seconds on a commodity 4-core Intel processor. This measured performance compares favorably with all previously published results. Additionally, the paper demonstrates performance scalability of the proposed sorting algorithm with respect to certain salient architectural features of modern chip multiprocessor (CMP) architectures, including SIMD width and core-count. Based on our analytical models of various architectural configurations, we see excellent scalability of our implementation with SIMD width scaling up to 16X wider than current SSE width of 128-bits, and CMP core-count scaling well beyond 32 cores. Cycle-accurate simulation of Intel’s upcoming x86 many-core Larrabee architecture confirms scalability of our proposed algorithm.
Keyphrases
efficient implementation multi-core simd cpu architecture simd width simd implementation various architectural configuration performance scalability sorting algorithm efficient multiway merge modern chip multiprocessor commodity 4-core intel processor customized implementation current cpu architecture computer science cycle-accurate simulation excellent scalability scalar version point number cmp core-count certain salient architectural feature input number current sse width various flavor memory bandwidth high-throughput database application 128-bit sse literature abounds x86 many-core larrabee architecture detailed analysis measured performance analytical model different architecture fundamental problem
