Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching

Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching (1996)

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by Eric Rotenberg , Steve Bennett , James E. Smith , Eric Rotenberg

Venue:	In Proceedings of the 29th International Symposium on Microarchitecture
Citations:	264 - 11 self

BibTeX

@INPROCEEDINGS{Rotenberg96tracecache:,
    author = {Eric Rotenberg and Steve Bennett and James E. Smith and Eric Rotenberg},
    title = {Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching},
    booktitle = {In Proceedings of the 29th International Symposium on Microarchitecture},
    year = {1996},
    pages = {24--34}
}

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Citations

745	Improving direct-mapped cache performance by the addition of a small fullyassociative cache and prefetch buffers - Jouppi - 1990
398	A study of branch prediction strategies - Smith - 1981
339	Limits of Instruction-Level Parallelism - Wall - 1991
264	Y.N.Patt. Alternative Implementations of Two-level Adaptive Branch Prediction - Yeh - 1992
232	Branch prediction strategies and branch target buffer design - Lee, Smith - 1984
175	Improving the accuracy of dynamic branch prediction using branch correlation - Pan, So, et al. - 1992
115	Optimization of instruction fetch mechanisms for high issue rates - Conte, Menezes, et al. - 1995
95	Increasing the Instruction Fetch Rate via Multiple Branch Prediction and a Branch Address Cache - Yeh, Marr, et al. - 1993
88	Ecient Program Tracing - Larus - 1993
82	Branch History Table Prediction of Moving Target Branches Due to Subroutine Returns - Kaeli, Emma - 1991
63	A comprehensive instruction fetch mechanism for a processor supporting speculative execution - Yeh, Patt - 1992
62	Instruction fetching: Coping with code bloat - Uhlig, Nagle, et al. - 1995
49	Hardware support for large atomic units in dynamically scheduled machines - Melvin, Shebanow, et al. - 1988
46	A ll-unit approach to multiple instruction issue - Franklin, Smotherman
38	Control Flow Prediction with Tree-Like Subgraphs for Superscalar Processors - Dutta, Franklin - 1995
31	The effect of speculatively updating branch history on branch prediction accuracy, revisited - Hao, Chang, et al. - 1994
21	Two-level adaptive branch prediction and instruction fetch mechanisms for high performance superscalar processors - Yeh - 1993
14	MIPS R10000 Uses Decoupled Architecture,’’ Microprocessor Report - Gwennap
6	Generalized History Table for Branch Prediction - Losq - 1982
2	Machine organization of the ibm rs/6000 processor - Grohoski - 1990