Abstract

The equivalence between redundant-binary to twos-complement number conversionand twos-complement addition is shown using a simple transform between the two number domains. As a consequence, all hardware architectures designed for eitheroperation may be easily adapted to implement the other.

Citations

16	A fast VLSI adder architecture - Srinivas, Parhi - 1992
2	Design of a high-performance IIR digital filter chip - Woods, McCanny - 1992
1	An 8.8-ns54x54-bit multiplier with high speed redundant binary architecure - Makino, Nakase, et al. - 1996