The Case for a Single-Chip Multiprocessor

The Case for a Single-Chip Multiprocessor (1996)

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by Kunle Olukotun , Basem A. Nayfeh , Lance Hammond , Ken Wilson , Kunyung Chang

Venue:	IEEE Computer
Citations:	326 - 5 self

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@INPROCEEDINGS{Olukotun96thecase,
    author = {Kunle Olukotun and Basem A. Nayfeh and Lance Hammond and Ken Wilson and Kunyung Chang},
    title = {The Case for a Single-Chip Multiprocessor},
    booktitle = {IEEE Computer},
    year = {1996},
    pages = {2--11}
}

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Abstract

Advances in IC processing allow for more microprocessor design options. The increasing gate density and cost of wires in advanced integrated circuit technologies require that we look for new ways to use their capabilities effectively. This paper shows that in advanced technologies it is possible to implement a single-chip multiproces-sor in the same area as a wide issue superscalar processor. We find that for applications with little parallelism the performance of the two microarchitectures is comparable. For applications with large amounts of parallelism at both the fine and coarse grained levels, the multiprocessor microarchitectnre outperforms the superscrdar architecture by a significant margin. Single-chip multiprocessor architectures have the advantage in that they offer localized imple-mentation of a high-clock rate processor for inherently sequential applications and low latency interprocessor communication for par-allel applications. 1

Citations

3633	Computer Architecture - A Quantitative Approach, 2nd Edition - Hennessy, Patterson - 1996
544	Combining branch predictors - McFarling - 1993
394	The MIPS R10000 Superscalar Microprocessor - Yeager - 1996
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257	Superscalar Microprocessor Design - Johnson - 1991
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118	High-bandwidth data memory systems for superscalar processors - Sohi, Franklin - 1991
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70	Computer Technology and Architecture: An Evolving Interaction - Hennessy, Jouppi - 1991
55	Compiler-directed page coloring for multiprocessors - Bugnion, Anderson, et al. - 1996
41	The SUIF Compiler for Scalable Parallel - Amarasinghe, Anderson, et al. - 1995
32	A 200-mhz 64-b dual-issue cmos microprocessor - Dobberpuhl - 1992
20	The SimOS approach - ROSENBLUM, HERROD, et al. - 1995
10	Register file considerations in dynamically scheduled processors - Farkas, Jouppi, et al. - 1996
10	The design and verification of the alphastation 600 5-series workstation - Zurawski, Murray, et al. - 1995
6	Evaluating alternatives for a multiprocessor microprocessor - Nayfeh, Hammond, et al. - 1996
6	Parallel operation - Thornton - 1964
4	Amarasinghe et.al., “Hot compilers for future hot chips,” presented at Hot Chips VII - unknown authors - 1995
4	A 300MHz 64b quad-issue CMOS microprocessor - Bowhill - 1995
2	The interconnect nightmare - Drappper - 1996
2	Combining branch predictors. WRL Technical Note TN-36 - McFarling - 1993
1	A quad issue out-of-order RISC - Lotz, Lesartre, et al. - 1996
1	Optimization of instmction fetch mechanisms for high issue rates - Conte, Menezes, et al. - 1996
1	Computer technolc)gy and architecture an evolving interaction - Hennessy, Jouppi - 1991
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1	approach - SimOS - 1995