DMCA
Timing-Driven Placement for General Cell Layout (1990)
| Citations: | 5 - 2 self |
BibTeX
@MISC{Ogawa90timing-drivenplacement,
author = {Yasushi Ogawa and Massoud Pedram and Ernest S. Kuh},
title = { Timing-Driven Placement for General Cell Layout },
year = {1990}
}
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Abstract
In this paper we present a hierarchical technique for the timing-driven placement of the general cells. We assume that maximum interconnection delays for nets are given. We transform these timing constraints to net length constraints using technology and process de-pendent parameters, circuit specific data such as input capacitance and output drivability, and the structural description of the circuit.. Next, we break the problem into a bottom-up clustering phase and a top-down enumerative placement phase. We consider both the natural connectivities and the net length constraints during the bottom-up phase in order to generate a hierarchical cluster tree. During the top-down placement phase, we place each node of the cluster tree so that the layout area and total interconnection length are minimized while satisfying the net length constraints.
Keyphrases
timing-driven placement general cell layout net length constraint general cell maximum interconnection delay hierarchical technique layout area top-down enumerative placement phase bottom-up phase natural connectivity cluster tree hierarchical cluster tree structural description circuit specific data output drivability timing constraint process de-pendent parameter top-down placement phase total interconnection length bottom-up clustering phase input capacitance
