Symbolic model checking for sequential circuit verification

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Symbolic model checking for sequential circuit verification (1994)

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by Jerry R. Burch , Edmund M. Clarke , David E. Long , Kenneth L. McMillan , David L. Dill

Venue:	IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
Citations:	271 - 12 self

BibTeX

@ARTICLE{Burch94symbolicmodel,
    author = {Jerry R. Burch and Edmund M. Clarke and David E. Long and Kenneth L. McMillan and David L. Dill},
    title = {Symbolic model checking for sequential circuit verification},
    journal = {IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS},
    year = {1994},
    volume = {13},
    number = {4},
    pages = {401--424}
}

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Abstract

The temporal logic model checking algorithm of Clarke, Emerson, and Sistla [17] is modified to represent state graphs using binary decision diagrams (BDD’s) [7] and partitioned trunsirion relations [lo], 1111. Because this representation captures some of the regularity in the state space of circuits with data path logic, we are able to verify circuits with an extremely large number of states. We demonstrate this new technique on a synchronous pipelined design with approximately 5 x 10^120 states. Our model checking algorithm handles full CTL with fairness constraints. Consequently, we are able to express a number of important liveness and fairness properties, which would otherwise not be expressible in CTL. We give empirical results on the performance of the algorithm applied to both synchronous and asynchronous circuits with data path logic.

Keyphrases

symbolic model sequential circuit verification data path logic new technique state space binary decision diagram state graph fairness constraint important liveness empirical result algorithm handle full ctl fairness property temporal logic model synchronous pipelined design large number asynchronous circuit partitioned trunsirion relation

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