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Complexity-Effective Issue Queue Design Under Load-Hit Speculation (2002)
| Venue: | In Proceedings of the Workshop Complexity-Effective Design, 2002 |
| Citations: | 8 - 0 self |
BibTeX
@INPROCEEDINGS{Moreshet02complexity-effectiveissue,
author = {Tali Moreshet and R. Iris Bahar},
title = {Complexity-Effective Issue Queue Design Under Load-Hit Speculation},
booktitle = {In Proceedings of the Workshop Complexity-Effective Design, 2002},
year = {2002}
}
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Abstract
Current trends in microprocessor designs indicate increasing pipeline depth in order to keep up with higher clock frequencies and increased architectural complexity. Speculatively issued instructions may be particularly sensitive to increase in pipeline depth, assuming that issued instructions are kept in the issue queue. In this paper, we evaluate the effectiveness of load hit speculation as pipeline depth increases. Effectiveness is measured in terms of performance improvement, issue queue size requirements and re-issue policy. Our results indicate that load hit speculation increases the percentage of issue queue instructions that are waiting to be re-issued, or replayed. This trend increases even more as pipelines become deeper. We propose an alternative, complexityeffective design for the issue queue, that takes into consideration the different utilization that load hit speculation demands from the issue queue. 1
Keyphrases
complexity-effective issue queue design load-hit speculation issue queue pipeline depth re-issue policy issue queue instruction pipeline depth increase issue queue size requirement speculation demand clock frequency complexityeffective design issued instruction current trend performance improvement microprocessor design different utilization architectural complexity
