DAISY: Dynamic Compilation for 100% Architectural Compatibility

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DAISY: Dynamic Compilation for 100% Architectural Compatibility (1997)

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by Kemal Ebcioglu , Erik R. Altman

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206 - 13 self

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@MISC{Ebcioglu97daisy:dynamic,
    author = {Kemal Ebcioglu and Erik R. Altman},
    title = {DAISY: Dynamic Compilation for 100% Architectural Compatibility},
    year = {1997}
}

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Abstract

Although VLIW architectures offer the advantages of simplicity of design and high issue rates, a major impediment to their use is that they are not compatible with the existing software base. We describe new simple hardware features for a VLIW machine we call DAISY (Dynamically Architected Instruction Set from Yorlaown). DAISY is specifically intended to emulate existing architectures, so that all existing software for an old architecture (including operating system kernel code) runs without changes on the VLIW. Each time a new fragment of code is executed for the first time, the code is translated to VLIW primitives, parallelized and saved in a portion of main memory not visible to the old architecture, by a Firtual Machine Monitor (software) residing in read only memory. Subsequent executions of the same fragment do not require a translation (unless cast out). We discuss the architectural requirements for such a VLIW, to deal with issues including self-modifying code, precise exceptions, and aggressive reordedng of memory references in the presence of strong MP consistency and memory mapped I/O. We have implemented the dynamic parallelization algorithms for the PowerPC architecture. The initial results show high degrees of instruction level parallelism with reasonable translation overhead and memory usage.

Keyphrases

dynamic compilation architectural compatibility old architecture high issue rate powerpc architecture main memory new fragment major impediment strong mp consistency memory reference memory usage software base dynamically architected instruction set high degree architectural requirement firtual machine monitor instruction level parallelism new simple hardware feature precise exception aggressive reordedng vliw machine first time subsequent execution initial result reasonable translation overhead self-modifying code dynamic parallelization algorithm vliw primitive

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