Loop Shifting and Compaction for the High-Level Synthesis Of Designs with Complex Control Flow

DMCA

Loop Shifting and Compaction for the High-Level Synthesis Of Designs with Complex Control Flow (2003)

Cached

Download Links

Other Repositories/Bibliography

DBLP

by Sumit Gupta , Nikil Dutt , Rajesh Gupta , Alex Nicolau

Venue:	In Georges Gielen and Joan Figueras, editors, Proceedings of Design, Automation and Test in Europe
Citations:	16 - 1 self

BibTeX

@INPROCEEDINGS{Gupta03loopshifting,
    author = {Sumit Gupta and Nikil Dutt and Rajesh Gupta and Alex Nicolau},
    title = {Loop Shifting and Compaction for the High-Level Synthesis Of Designs with Complex Control Flow},
    booktitle = {In Georges Gielen and Joan Figueras, editors, Proceedings of Design, Automation and Test in Europe},
    year = {2003},
    pages = {114--119},
    publisher = {IEEE Computer Society}
}

OpenURL

Abstract

Emerging embedded system applications in multimedia and image processing are characterized by complex control flow consisting of deeply nested conditionals and loops. Effective hardware generation using high-level synthesis tools for these applications requires the ability to move code across condition and loop boundaries and exploit the algorithmic parallelism. Traditional loop transformations such as loop unrolling and loop pipelining have been shown to be effective only in the presence of substantive resource allocation. In case of high level synthesis, it has been shown earlier that straightforward exposition of maximum parallelism does not yield the highest performance designs, due to the control and multiplexing overheads. In this paper, we present a technique that implicitly and incrementally exploits loop level parallelism across iterations 2aa by shifting and compacting operations across loop iterations. We demonstrate the effectiveness of this technique, even under tight resource constraints, in terms of circuit performance, controller size and total size of the design. We have implemented loop shifting within a parallelizing high-level synthesis system, Spark. We achieve improvements of up to 20 % in input-to-output delay in the synthesized circuit for experiments on designs derived from two moderately complex industrial-strength applications, MPEG-1 and the GIMP image processing tool.

Keyphrases

complex control flow high-level synthesis loop shifting high level synthesis traditional loop transformation maximum parallelism loop unrolling performance design circuit performance algorithmic parallelism embedded system application total size image processing substantive resource allocation synthesized circuit effective hardware generation loop boundary loop level parallelism complex industrial-strength application controller size loop pipelining input-to-output delay loop iteration high-level synthesis tool gimp image processing tool straightforward exposition tight resource constraint high-level synthesis system

DMCA