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Graph coloring vs. optimal register allocation for optimizing compilers (2003)
| Venue: | In Joint Modular Languages Conference |
| Citations: | 11 - 1 self |
BibTeX
@INPROCEEDINGS{Hirnschrott03graphcoloring,
author = {Ulrich Hirnschrott and Andreas Krall and Bernhard Scholz},
title = {Graph coloring vs. optimal register allocation for optimizing compilers},
booktitle = {In Joint Modular Languages Conference},
year = {2003},
pages = {202--213},
publisher = {Springer Press}
}
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Abstract
Abstract. Optimizing compilers play an important role for the efficient execution of programs written in high level programming languages. Current microprocessors impose the problem that the gap between processor cycle time and memory latency increases. In order to fully exploit the potential of processors, nearly optimal register allocation is of paramount importance. In the predominance of the x86 architecture and in the increased usage of high-level programming languages for embedded systems peculiarities and irregularities in their register sets have to be handled. These irregularities makes the task of register allocation for optimizing compilers more difficult than for regular architectures and register files. In this article we show how optimistic graph coloring register allocation can be extended to handle these irregularities. Additionally we present an exponential algorithm which in most cases can compute an optimal solution for register allocation and copy elimination. These algorithms are evaluated on a virtual processor architecture modeling two and three operand architectures with different register file sizes. The evaluation demonstrates that the heuristic graph coloring register allocator comes close to the optimal solution for large register files, but performs badly on small register files. For small register files the optimal algorithm is fast enough to replace a heuristic algorithm. 1
Keyphrases
optimal register allocation optimal solution register allocation important role high level programming language efficient execution large register file register file current microprocessor small register high-level programming language small register file different register file size register set optimal algorithm exponential algorithm operand architecture x86 architecture copy elimination heuristic graph register allocator regular architecture virtual processor architecture paramount importance memory latency increase heuristic algorithm optimistic graph processor cycle time embedded system peculiarity increased usage
