Modeling the effect of technology trends on the soft error rate of combinational logic

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Modeling the effect of technology trends on the soft error rate of combinational logic (2002)

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by Premkishore Shivakumar , Michael Kistler , Stephen W. Keckler , Doug Burger , Lorenzo Alvisi , Ibm Technical , Contacts John Keaty , Rob Bell , Ram Rajamony

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374 - 8 self

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@INPROCEEDINGS{Shivakumar02modelingthe,
    author = {Premkishore Shivakumar and Michael Kistler and Stephen W. Keckler and Doug Burger and Lorenzo Alvisi and Ibm Technical and Contacts John Keaty and Rob Bell and Ram Rajamony},
    title = {Modeling the effect of technology trends on the soft error rate of combinational logic},
    booktitle = {},
    year = {2002},
    pages = {389--398}
}

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Abstract

This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to-end model that enables us to compute the soft error rates (SER) for existing and future microprocessor-style designs. The model captures the effects of two important masking phenomena, electrical masking and latchingwindow masking, which inhibit soft errors in combinational logic. We quantify the SER in combinational logic and latches for feature sizes from 600nm to 50nm and clock rates from 16 to 6 fan-out-of-4 delays. Our model predicts that the SER per chip of logic circuits will increase eight orders of magnitude by the year 2011 and at that point will be comparable to the SER per chip of unprotected memory elements. Our result emphasizes the need for computer system designers to address the risks of SER in logic circuits in future designs. 1

Keyphrases

combinational logic soft error rate logic circuit technology trend soft error future design future microprocessor-style design end-to-end model feature size technology scaling latchingwindow masking fan-out-of-4 delay electrical masking computer system designer unprotected memory element microarchitectural trend cmos memory

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