Register Binding for FPGAs with Embedded Memory

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Register Binding for FPGAs with Embedded Memory

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by Hassan Al Atat, et al.

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BibTeX

@MISC{Atat_registerbinding,
    author = {Hassan Al Atat and et al.},
    title = {Register Binding for FPGAs with Embedded Memory},
    year = {}
}

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Abstract

The trend in new state-of-the-art FPGAs is to have large amounts of on-chip embedded memory blocks. These memory blocks are used to hold the input/output data for various applications. Existing register binding techniques in high-level synthesis aim at minimizing the storage requirements of circuits by sharing variables among registers and thus minimizing the required number of registers for a specific design. In this paper, a new technique is proposed that makes use of the existing embedded memory blocks and maps variables to these blocks. The proposed memory binding approach gives considerable performance increase over the existing register binding techniques. The memory binding technique resulted in up to 57 % savings in the total chip area (number of Logic Cells/Elements occupied on the FPGA) over the old register binding techniques for a small resource bag and up to 6 % savings for a large resource bag.

Keyphrases

embedded memory register binding memory block small resource bag high-level synthesis aim on-chip embedded memory block input output data new technique memory binding technique logic cell element new state-of-the-art fpgas storage requirement various application required number old register proposed memory map variable total chip area specific design large amount considerable performance increase large resource bag

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