Design of Embedded Systems: Formal Models, Validation, and Synthesis

Design of Embedded Systems: Formal Models, Validation, and Synthesis (1999)

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by S. Edwards , L. Lavagno , E. A. Lee , A. Sangiovanni-Vincentelli

Venue:	PROCEEDINGS OF THE IEEE
Citations:	124 - 9 self

BibTeX

@INPROCEEDINGS{Edwards99designof,
    author = {S. Edwards and L. Lavagno and E. A. Lee and A. Sangiovanni-Vincentelli},
    title = {Design of Embedded Systems: Formal Models, Validation, and Synthesis},
    booktitle = {PROCEEDINGS OF THE IEEE},
    year = {1999},
    pages = {366--390},
    publisher = {}
}

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Abstract

This paper addresses the design of reactive real-time embedded systems. Such systems are often heterogeneous in implementation technologies and design styles, for example by combining hardware ASICs with embedded software. The concurrent design process for such embedded systems involves solving the specification, validation, and synthesis problems. We review the variety of approaches to these problems that have been taken.

Keyphrases

embedded system formal model embedded software design style reactive real-time hardware asics concurrent design process implementation technology synthesis problem