Limits of instruction-level parallelism

Limits of instruction-level parallelism (1991)

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by David W. Wall

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339 - 7 self

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@INPROCEEDINGS{Wall91limitsof,
    author = {David W. Wall},
    title = {Limits of instruction-level parallelism},
    booktitle = {},
    year = {1991},
    pages = {176--188}
}

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Abstract

research relevant to the design and application of high performance scientific computers. We test our ideas by designing, building, and using real systems. The systems we build are research prototypes; they are not intended to become products. There two other research laboratories located in Palo Alto, the Network Systems

Citations

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234	A comparison of dynamic branch predictors that use two levels of branch history - Yeh, Patt - 1993
232	Branch prediction strategies and branch target buffer design - Lee, Smith - 1984
192	Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines - Jouppi, Wall - 1989
175	Improving the accuracy of dynamic branch prediction using branch correlation - Pan, So, et al. - 1992
169	Global register allocation at link time - Wall - 1986
140	A Practical Sys-tem for Intermodule Code Optimization at LinkTime - Srivastava, Wall - 1993
140	Predicting program behavior using real or estimated pro les - Wall - 1991
112	S.S.: Efficient instruction scheduling for a pipelined architecture - Gibbons, Muchnick - 1986
103	Code scheduling and register allocation in large basic blocks - Goodman, Hsu - 1988
99	Integrated Register Allocation and Instruction Scheduling for RISCs - Bradlee, Eggers, et al. - 1991
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94	Tradeoffs in two-level on-chip caching - Jouppi, Wilton - 1994
90	Link-Time Optimization of Address Calculation on a 64-bit Architecture - Srivastava, Wall - 1994
87	Systems for late code modification - Wall - 1992
83	Abstractions for recursive pointer data structures: improving the analysis and transformation of imperative programs - Hendren, Hummell, et al. - 1992
74	Long Address Traces from RISC Machines: Generation and Analysis - Borg, Kessler, et al. - 1989
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53	Experience with a Software-defined Machine Architecture - Wall - 1991
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21	Efficient Generation of Test Patterns Using Boolean Satisfiablilty." "Available Instruction-Level Parallelism for SuperTracy Larrabee. scalar and - Jouppi, Wall - 1990
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