A Flexible Heterogeneous Multi-Core Architecture

DMCA

A Flexible Heterogeneous Multi-Core Architecture

Cached

Download Links

Other Repositories/Bibliography

DBLP

by Miquel Pericàs , Adrian Cristal , Francisco J. Cazorla , Ruben González , Daniel A. Jiménez , Mateo Valero

Citations:

22 - 0 self

BibTeX

@MISC{Pericàs_aflexible,
    author = {Miquel Pericàs and Adrian Cristal and Francisco J. Cazorla and Ruben González and Daniel A. Jiménez and Mateo Valero},
    title = {A Flexible Heterogeneous Multi-Core Architecture},
    year = {}
}

OpenURL

Abstract

Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a challenge as application mixes in this environment are nonuniform. Thus, multi-core processors should be flexible enough to provide high throughput for uniform parallel applications as well as high performance for more general workloads. Heterogeneous architectures are a first step in this direction, but partitioning remains static and only roughly fits application requirements. This paper proposes the Flexible Heterogeneous MultiCore processor (FMC), the first dynamic heterogeneous multi-core architecture capable of reconfiguring itself to fit application requirements without programmer intervention. The basic building block of this microarchitecture is a scalable, variable-size window microarchitecture that exploits the concept of Execution Locality to provide large-window capabilities. This allows to overcome the memory wall for applications with high memory-level parallelism (MLP). The microarchitecture contains a set of small and fast cache processors that execute high locality code and a network of small in-order memory engines that together exploit low locality code. Single-threaded applications can use the entire network of cores while multi-threaded applications can efficiently share the resources. The sizing of critical structures remains small enough to handle current power envelopes. In single-threaded mode this processor is able to outperform previous state-of-the-art high-performance processor research by 12 % on SpecFP. We show how in a quadthreaded/quad-core environment the processor outperforms a statically allocated configuration in both throughput and 1 harmonic mean, two commonly used metrics to evaluate SMT performance, by around 2-4%. This is achieved while using a very simple sharing algorithm. 1

Keyphrases

flexible heterogeneous multi-core architecture multi-core processor application requirement thread-level parallelism instruction-level parallelism application mix heterogeneous architecture memory wall entire network variable-size window microarchitecture harmonic mean first step flexible heterogeneous multicore processor general workload programmer intervention high performance quadthreaded quad-core environment basic building block uniform parallel application small in-order memory engine first dynamic heterogeneous multi-core architecture large-window capability fast cache processor previous state-of-the-art high-performance processor research critical structure multi-threaded application individual application single-threaded mode high throughput single-threaded application high locality code smt performance current power envelope high memory-level parallelism exploit low locality code execution locality

DMCA