Runahead execution: An alternative to very large instruction windows for out-of-order processors

DMCA

Runahead execution: An alternative to very large instruction windows for out-of-order processors (2003)

Cached

Download Links

Other Repositories/Bibliography

DBLP

by Onur Mutlu , Jared Stark , Chris Wilkerson , Yale N. Patt

Venue:	In HPCA-9
Citations:	175 - 22 self

BibTeX

@INPROCEEDINGS{Mutlu03runaheadexecution:,
    author = {Onur Mutlu and Jared Stark and Chris Wilkerson and Yale N. Patt},
    title = {Runahead execution: An alternative to very large instruction windows for out-of-order processors},
    booktitle = {In HPCA-9},
    year = {2003},
    pages = {129--140}
}

OpenURL

Abstract

Today’s high performance processors tolerate long latency operations by means of out-of-order execution. However, as latencies increase, the size of the instruction window must increase even faster if we are to continue to tolerate these latencies. We have already reached the point where the size of an instruction window that can handle these latencies is prohibitively large, in terms of both design complexity and power consumption. And, the problem is getting worse. This paper proposes runahead execution as an effective way to increase memory latency tolerance in an out-of-order processor, without requiring an unreasonably large instruction window. Runahead execution unblocks the instruction window blocked by long latency operations allowing the processor to execute far ahead in the program path. This results in data being prefetched into caches long before it is needed. On a machine model based on the Intel R ○ Pentium R ○ 4 processor, having a 128-entry instruction window, adding runahead execution improves the IPC (Instructions Per Cycle) by 22 % across a wide range of memory intensive applications. Also, for the same machine model, runahead execution combined with a 128-entry window performs within 1 % of a machine with no runahead execution and a 384-entry instruction window. 1.

Keyphrases

runahead execution out-of-order processor large instruction window instruction window machine model long latency operation 128-entry window performs instruction per cycle design complexity 128-entry instruction window memory latency tolerance power consumption high performance processor program path memory intensive application 384-entry instruction window latency increase wide range effective way intel pentium out-of-order execution

DMCA