Power Aware Page Allocation

DMCA

Power Aware Page Allocation (2000)

Cached

Download Links

Other Repositories/Bibliography

DBLP

by Alvin R. Lebeck , Xiaobo Fan , Heng Zeng , Carla Ellis

Venue:	In Architectural Support for Programming Languages and Operating Systems
Citations:	189 - 10 self

BibTeX

@INPROCEEDINGS{Lebeck00poweraware,
    author = {Alvin R. Lebeck and Xiaobo Fan and Heng Zeng and Carla Ellis},
    title = {Power Aware Page Allocation},
    booktitle = {In Architectural Support for Programming Languages and Operating Systems},
    year = {2000},
    pages = {105--116}
}

OpenURL

Abstract

One of the major challenges of post-PC computing is the need to reduce energy consumption, thereby extending the lifetime of the batteries that p ower these mobile devices. Memory is a particularly important tar get for e orts to improve energy e ciency. Memory technolo gy is becoming available that o ers power management featur es such as the ability to put individual chips in any one of several di erent power modes. In this paper we explor e the interaction of page plac ement with static and dynamic hardware policies to exploit these emer ginghardwar efeatur es. In p articular, we c onsider p age allo cation p olicies that ancbe employed by an informed operating system to complement the hardware power management strategies. We perform experiments using two complementary simulation envir onments: a tracedriven simulator with workload traces that are representative of mobile computing and an execution-driven simulator with a detaile d processor/memory model and a more memoryintensive set of benchmarks (SPEC2000). Our r esults make a compelling case for a cooperative hardwar e/software approach for exploiting power-aware memory, with down to as little as 45 % of the Energy Delay for the best static policy and 1 % to 20 % of the Ener gyDelay for a traditional fullpower memory. 1.

Keyphrases

power aware page allocation energy ciency energy consumption complementary simulation envir onments hardware power management strategy tracedriven simulator important tar get post-pc computing energy delay detaile processor memory model compelling case er power management featur e cooperative hardwar software approach mobile device ginghardwar efeatur e execution-driven simulator age allo cation olicies memoryintensive set memory technolo gy major challenge operating system workload trace ener gydelay dynamic hardware policy static policy page plac ement individual chip erent power mode power-aware memory

DMCA