Cooperative caching for chip multiprocessors (2006)
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| Venue: | In Proceedings of the 33nd Annual International Symposium on Computer Architecture |
| Citations: | 87 - 1 self |
BibTeX
@INPROCEEDINGS{Chang06cooperativecaching,
author = {Jichuan Chang},
title = {Cooperative caching for chip multiprocessors},
booktitle = {In Proceedings of the 33nd Annual International Symposium on Computer Architecture},
year = {2006},
pages = {264--276}
}
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Abstract
Chip multiprocessor (CMP) systems have made the on-chip caches a critical resource shared among co-scheduled threads. Limited off-chip bandwidth, increasing on-chip wire delay, destructive inter-thread interference, and diverse workload characteristics pose key design challenges. To address these challenge, we propose CMP cooperative caching (CC), a unified framework to efficiently organize and manage on-chip cache resources. By forming a globally managed, shared cache using cooperative private caches. CC can effectively support two important caching applications: (1) reduction of average memory access latency and (2) isolation of destructive inter-thread interference. CC reduces the average memory access latency by balancing between cache latency and capacity opti-mizations. Based private caches, CC naturally exploits their access latency benefits. To improve the effective cache capacity, CC forms a “shared ” cache using replication control and LRU-based global replacement policies. Via cooperation throttling, CC provides a spectrum of caching behaviors between the two extremes of private and shared caches, thus enabling dynamic adaptation to suit workload requirements. We show that CC can achieve a robust performance advantage over private and shared cache schemes across different processor, cache and memory configurations, and a wide selection of multithreaded and multiprogrammed
