Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor

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Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor (1996)

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by Dean M. Tullsen , Susan J. Eggers , Joel S. Emer , Henry M. Levy , Jack L. Lo , Rebecca L. Stamm

Venue:	IN PROCEEDINGS OF THE 23RD ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE
Citations:	370 - 37 self

BibTeX

@INPROCEEDINGS{Tullsen96exploitingchoice:,
    author = {Dean M. Tullsen and Susan J. Eggers and Joel S. Emer and Henry M. Levy and Jack L. Lo and Rebecca L. Stamm},
    title = {Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor},
    booktitle = {IN PROCEEDINGS OF THE 23RD ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE},
    year = {1996},
    pages = {191--202},
    publisher = {}
}

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Abstract

Simultaneous multithreading is a technique that permits multiple independent threads to issue multiple instructions each cycle. In previous work we demonstrated the performance potential of simultaneous multithreading, based on a somewhat idealized model. In this paper we show that the throughput gains from simultaneous multithreading can be achieved without extensive changes to a conventional wide-issue superscalar, either in hardware structures or sizes. We present an architecture for simultaneous multithreading that achieves three goals: (1) it minimizes the architectural impact on the conventional superscalar design, (2) it has minimal performance impact on a single thread executing alone, and (3) it achieves significant throughput gains when running multiple threads. Our simultaneous multithreading architecture achieves a throughput of 5.4 instructions per cycle, a 2.5-fold improvement over an unmodified superscalar with similar hardware resources. This speedup is enhanced by an advantage of multithreading previously unexploited in other architectures: the ability to favor for fetch and issue those threads most efficiently using the processor each cycle, thereby providing the “best” instructions to the processor.

Keyphrases

simultaneous multithreading implementable simultaneous multithreading processor instruction fetch unmodified superscalar 5-fold improvement single thread multiple instruction similar hardware resource conventional wide-issue superscalar throughput gain architectural impact conventional superscalar design significant throughput gain hardware structure simultaneous multithreading architecture multiple independent thread minimal performance impact idealized model previous work extensive change performance potential

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