Reducing the Complexity of the Register File in Dynamic Superscalar Processors

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Reducing the Complexity of the Register File in Dynamic Superscalar Processors (2001)

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by Rajeev Balasubramonian , Sandhya Dwarkadas , David H. Albonesi

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@MISC{Balasubramonian01reducingthe,
    author = {Rajeev Balasubramonian and Sandhya Dwarkadas and David H. Albonesi},
    title = {Reducing the Complexity of the Register File in Dynamic Superscalar Processors},
    year = {2001}
}

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Abstract

Dynamic superscalar processors execute multiple instructions out-of-order by looking for independent operations within a large window. The number of physical registers within the processor has a direct impact on the size of this window as most in-flight instructions require a new physical register at dispatch. A large multiported register file helps improve the instruction-level parallelism (ILP), but may have a detrimental effect on clock speed, especially in future wire-limited technologies. In this paper, we propose a register file organization that reduces register file size and port requirements for a given amount of ILP. We use a two-level register file organization to reduce register file size requirements, and a banked organization to reduce port requirements. We demonstrate empirically that the resulting register file organizations have reduced latency and (in the case of the banked organization) energy requirements for similar instructions per cycle (IPC) performance and improved instructions per second (IPS) performance in comparison to a conventional monolithic register file. The choice of organization is dependent on design goals.

Keyphrases

dynamic superscalar processor register file banked organization port requirement detrimental effect instruction-level parallelism file size new physical register register file organization multiple instruction out-of-order direct impact register file size requirement conventional monolithic register file resulting register file organization design goal physical register large multiported register file similar instruction improved instruction large window future wire-limited technology two-level register file organization independent operation in-flight instruction clock speed energy requirement

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