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Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling (2002)
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| Venue: | In Proceedings of the 8th International Symposium on High-Performance Computer Architecture |
| Citations: | 108 - 13 self |
BibTeX
@INPROCEEDINGS{Semeraro02energy-efficientprocessor,
author = {Greg Semeraro and Grigorios Magklis and Rajeev Balasubramonian and David H. Albonesi and Sandhya Dwarkadas and Hya Dwarkadas and Michael L. Scott},
title = {Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling},
booktitle = {In Proceedings of the 8th International Symposium on High-Performance Computer Architecture},
year = {2002},
pages = {29--40}
}
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Abstract
As clock frequency increases and feature size decreases, clock distribution and wire delays present a growing challenge to the designers of singly-clocked, globally synchronous systems. We describe an alternative approach, which we call a Multiple Clock Domain (MCD) processor, in which the chip is divided into several (coarse-grained) clock domains, within which independent voltage and frequency scaling can be performed. Boundaries between domains are chosen to exploit existing queues, thereby minimizing inter-domain synchronization costs. We propose four clock domains, corresponding to the front end (including L1 instruction cache), integer units, floating point units, and load-store units (including L1 data cache and L2 cache). We evaluate this design using a simulation infrastructure based on SimpleScalar and Wattch. In an attempt to quantify potential energy savings independent of any particular on-line control strategy, we use off-line analysis of traces from a single-speed run of each of our benchmark applications to identify profitable reconfiguration points for a subsequent dynamic scaling run. Dynamic runs incorporate a detailed model of inter-domain synchronization delays, with latencies for intra-domain scaling similar to the whole-chip scaling latencies of Intel XScale and Transmeta LongRun technologies. Using applications from the MediaBench, Olden, and SPEC2000 benchmark suites, we obtain an average energy-delay product improvement of 20% with MCD compared to a modest 3% savings from voltage scaling a single clock and voltage system.
Keyphrases
frequency scaling dynamic voltage clock domain potential energy saving spec2000 benchmark suite profitable reconfiguration point average energy-delay product improvement l1 instruction cache inter-domain synchronization delay subsequent dynamic scaling run whole-chip scaling latency synchronous system clock frequency increase benchmark application simulation infrastructure feature size decrease intel xscale multiple clock domain l2 cache point unit voltage system integer unit intra-domain scaling clock distribution off-line analysis transmeta longrun technology l1 data cache detailed model single clock inter-domain synchronization cost wire delay particular on-line control strategy front end load-store unit alternative approach single-speed run independent voltage
