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The Design of the Node for the Single Chip Message Passing (SCMP) Parallel Computer (2004)
BibTeX
@MISC{Bucciero04thedesign,
author = {Mark Bucciero and Jim Armstrong and Thomas Martin and Mark Bucciero and James M. Baker},
title = {The Design of the Node for the Single Chip Message Passing (SCMP) Parallel Computer},
year = {2004}
}
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Abstract
Current processor designs use additional transistors to add functionality that improves performance. These features tend to exploit instruction level parallelism. However, a point of diminishing returns has been reached in this effort. Instead, these additional transistors could be used to take advantage of thread level parallelism (TLP). This type of parallelism focuses on hundreds of instructions, rather than single instructions, executing in parallel. Additionally, as transistor sizes shrink, the wires on a chip become thinner. Fabricating a thinner wire means increasing the resistance and thus, the latency of that wire. In fact, in the near future, a signal may not reach a portion of the chip in a single clock cycle. So, in future designs, it will be important to limit the length of the wires on a chip. The SCMP parallel computer is a new architecture that is made up of small processing elements, called nodes, which are connected in a 2-D mesh with nearest neighbor connections. Nodes communicate with one another, via message passing, through a network, which uses dimension order worm-hole routing. To support TLP, each node is
Keyphrases
single chip message passing parallel computer additional transistor future design current processor design near future small processing element new architecture chip become thinner nearest neighbor connection thinner wire scmp parallel computer node communicate single instruction parallelism focus thread level parallelism 2-d mesh single clock cycle dimension order worm-hole routing instruction level parallelism message passing
