Abstract

ABSTRACT The performance analysis of various multiplier architectures are compared in terms of power, area, delay in the view of low power applications. In this paper, design of array multiplier, Baugh-Wooley multipliers and Braun Multiplier are presented by using CLRCL (Complementary & Level Restoring Carry Logic) Adder. The multipliers presented in this paper were all simulated for 4 bit data. The comparison is made on the basis of Power consumption. To design an efficient integrated circuit in terms of power and area has become a challenging task in modern VLSI design field. In this work, multipliers are designed by using CLRCL Adder and gives better area minimization compared to multipliers using Conventional full adder. Tanner EDA tool was used for simulating designs in the 250nm technologies.