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A High-Speed Link Layer Architecture for Low Latency and Memory Cost Reduction (2007)
BibTeX
@MISC{Lee07ahigh-speed,
author = {Jaesung Lee and Hyuk-jae Lee and Chanho Lee},
title = {A High-Speed Link Layer Architecture for Low Latency and Memory Cost Reduction},
year = {2007}
}
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Abstract
This paper presents the design and implementation of the InfiniBand link layer with special efforts made for packet latency reduction and buffer space optimization. The link layer is designed to avoid any architectural conflict while its components are executed in parallel as far as possible. For highspeed packet processing with the various quality of service supports required by InfiniBand, three candidates for packet receiving architecture are investigated. The maximum and minimum delays from an input to an output of a switch adopting each of the three candidates is estimated by mathematically modeling the switch delays. Then, the candidate architecture with the best performance is chosen, and a novel first-in first-out (FIFO) is designed to efficiently implement the chosen architecture. Simulation results show that the chosen architecture achieves the least packet latency and uses the least memory space among the three candidates. The link layer core is implemented in an InfiniBand host channel adapter system-on-chip called KINCA.
Keyphrases
memory cost reduction low latency high-speed link layer architecture chosen architecture architectural conflict switch delay packet latency reduction minimum delay service support candidate architecture packet receiving architecture various quality infiniband link layer special effort novel first-in first-out simulation result infiniband host channel adapter system-on-chip memory space packet latency link layer core space optimization highspeed packet processing link layer
