First-order incremental block-based statistical timing analysis

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First-order incremental block-based statistical timing analysis (2004)

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by C. Visweswariah , K. Ravindran , K. Kalafala , S. G. Walker , S. Narayan

Venue:	In DAC
Citations:	192 - 6 self

BibTeX

@INPROCEEDINGS{Visweswariah04first-orderincremental,
    author = {C. Visweswariah and K. Ravindran and K. Kalafala and S. G. Walker and S. Narayan},
    title = {First-order incremental block-based statistical timing analysis},
    booktitle = {In DAC},
    year = {2004},
    pages = {331--336}
}

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Abstract

Variability in digital integrated circuits makes timing verification an extremely challenging task. In this paper, a canonical first order delay model is proposed that takes into account both correlated and independent randomness. A novel linear-time block-based statistical timing algorithm is employed to propagate timing quantities like arrival times and required arrival times through the timing graph in this canonical form. At the end of the statistical timing, the sensitivities of all timing quantities to each of the sources of variation are available. Excessive sensitivities can then be targeted by manual or automatic optimization methods to improve the robustness of the design. The statistical timing analysis is incremental, and is therefore suitable for use in the inner loop of physical synthesis or other optimization programs. The second novel contribution of this paper is the computation of local and global criticality probabilities. For a very small cost in CPU time, the probability of each edge or node of the timing graph being critical is computed. These criticality probabilities provide additional useful diagnostics to synthesis, optimization, test generation and path enumeration programs. Numerical results are presented on industrial ASIC chips with over two million logic gates. 1.

Keyphrases

arrival time timing quantity timing graph inner loop numerical result test generation small cost logic gate canonical form digital integrated circuit excessive sensitivity automatic optimization method criticality probability optimization program path enumeration program industrial asic chip cpu time statistical timing analysis physical synthesis independent randomness second novel contribution challenging task canonical first order delay model global criticality probability additional useful diagnostics statistical timing

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