SIS: A System for Sequential Circuit Synthesis

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SIS: A System for Sequential Circuit Synthesis (1992)

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by Ellen M. Sentovich , Kanwar Jit Singh , Luciano Lavagno , Cho Moon , Rajeev Murgai , Alexander Saldanha , Hamid Savoj , Paul R. Stephan , Robert K. Brayton , Alberto Sangiovanni-Vincentelli

Citations:

526 - 44 self

BibTeX

@TECHREPORT{Sentovich92sis:a,
    author = {Ellen M. Sentovich and Kanwar Jit Singh and Luciano Lavagno and Cho Moon and Rajeev Murgai and Alexander Saldanha and Hamid Savoj and Paul R. Stephan and Robert K. Brayton and Alberto Sangiovanni-Vincentelli},
    title = {SIS: A System for Sequential Circuit Synthesis},
    institution = {},
    year = {1992}
}

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Abstract

SIS is an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table, a signal transition graph, or a logic-level description of a sequential circuit, it produces an optimized net-list in the target technology while preserving the sequential input-output behavior. Many different programs and algorithms have been integrated into SIS, allowing the user to choose among a variety of techniques at each stage of the process. It is built on top of MISII [5] and includes all (combinational) optimization techniques therein as well as many enhancements. SIS serves as both a framework within which various algorithms can be tested and compared, and as a tool for automatic synthesis and optimization of sequential circuits. This paper provides an overview of SIS. The first part contains descriptions of the input specification, STG (state transition graph) manipulation, new logic optimization and verification algorithms, ASTG (asynchronous signal transition graph) manipulation, and synthesis for PGA’s (programmable gate arrays). The second part contains a tutorial example illustrating the design process using SIS.

Keyphrases

sequential circuit sequential circuit synthesis second part new logic optimization first part many different program input specification various algorithm state transition table programmable gate array design process sequential input-output behavior optimization technique automatic synthesis logic-level description tutorial example target technology signal transition graph optimized net-list verification algorithm interactive tool many enhancement state transition graph asynchronous signal transition graph

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