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Configurable isolation: building high availability systems with commodity multi-core processors (2007)
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| Venue: | In Proceedings of the 34th Annual International Symposium on Computer Architecture |
| Citations: | 51 - 1 self |
BibTeX
@INPROCEEDINGS{Aggarwal07configurableisolation:,
author = {Nidhi Aggarwal and Parthasarathy Ranganathan},
title = {Configurable isolation: building high availability systems with commodity multi-core processors},
booktitle = {In Proceedings of the 34th Annual International Symposium on Computer Architecture},
year = {2007},
pages = {470--481},
publisher = {ACM Press}
}
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Abstract
High availability is an increasingly important requirement for enterprise systems, often valued more than performance. Systems designed for high availability typically use redundant hardware for error detection and continued uptime in the event of a failure. Chip multiprocessors with an abundance of identical resources like cores, cache and interconnection networks would appear to be ideal building blocks for implementing high availability solutions on chip. However, doing so poses significant challenges with respect to error containment and faulty component replacement. Increasing silicon and transient fault rates with future technology scaling exacerbate the problem. This paper proposes a novel, costeffective, architecture for high availability systems built from future multi-core processors. We propose a new chip multiprocessor architecture that provides configurable isolation for fault containment and component retirement, based upon cost-effective modifications to commodity designs. The design is evaluated for a state-of-the-art industrial fault model and the proposed architecture is shown to provide effective fault isolation and graceful degradation even when the failure rate is high.
Keyphrases
configurable isolation building high availability system commodity multi-core processor high availability future multi-core processor enterprise system cost-effective modification interconnection network significant challenge error detection state-of-the-art industrial fault model chip multiprocessor future technology failure rate transient fault rate high availability solution high availability system commodity design faulty component replacement identical resource important requirement new chip multiprocessor architecture fault containment component retirement ideal building block graceful degradation effective fault isolation use redundant hardware
