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High-Level Power Analysis for On-Chip Networks (2004)
by
Noel Eisley
,
Li-Shiuan Peh
| Citations: | 41 - 7 self |
BibTeX
@MISC{Eisley04high-levelpower,
author = {Noel Eisley and Li-Shiuan Peh},
title = {High-Level Power Analysis for On-Chip Networks},
year = {2004}
}
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Abstract
As on-chip networks become prevalent in multiprocessor systemson -a-chip and multi-core processors, they will be an integral part of the design flow of such systems. With power increasingly the primary constraint in chips, the tool chain in systems design, from simulation infrastructures to compilers and synthesis frameworks, needs to take network power into account, motivating the need for early-stage communication power analysis.
