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Design and implementation of a high speed microprocessor simulator BurstScalar (2004)
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| Venue: | In Proc. 12th IEEE/ACM Intl. Symp. Modeling, Analysis and Simulation of Computer and Telecommunication Systems |
| Citations: | 1 - 1 self |
BibTeX
@INPROCEEDINGS{Nakada04designand,
author = {Takashi Nakada and Hiroshi Nakashima},
title = {Design and implementation of a high speed microprocessor simulator BurstScalar},
booktitle = {In Proc. 12th IEEE/ACM Intl. Symp. Modeling, Analysis and Simulation of Computer and Telecommunication Systems},
year = {2004},
pages = {364--372}
}
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Abstract
This paper describes the design and implementation of our high speed simulator for out-of-order microprocessors named BurstScalar. The simulator is based on the well-known SimpleScalar simulator but its execution speed is ac-celerated by computation reuse technique. Each time a loop is iterated, BurstScalar consults its state transition table to examine whether the iteration turns the microarchitectural state into what has already occurred. If the behavior of the iteration matches a state transition table entry, we reuse the complicated computation for out-of-order microarchi-tectural simulation by simply following the transition arc registered in the table. Moreover, in order to minimize the overhead of the reuse, we apply the reuse technique only to loops with enough number of iterations. This loop se-lection is performed by an instruction level pre-execution which only costs 1/10 to 1/100 of out-of-order cycle accu-rate simulation. The evaluation of BurstScalar with SPEC CPU95 benchmarks proves its efficiency showing up to 5.1 and 2.3-fold speedups over SimpleScalar for SPECfp and SPECint respectively, and 2.6 and 1.5-fold in average. 1.
Keyphrases
high speed microprocessor simulator burstscalar out-of-order microprocessor microarchitectural state well-known simplescalar simulator 3-fold speedup out-of-order microarchi-tectural simulation loop se-lection state transition table spec cpu95 state transition table entry reuse technique instruction level pre-execution execution speed high speed simulator computation reuse technique out-of-order cycle accu-rate simulation transition arc complicated computation enough number
