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FastMP: A Multi-core Simulation Methodology (2006)
| Venue: | The annual Workshop on Modeling, Benchmarking and Simulation (MOBS |
| Citations: | 19 - 0 self |
BibTeX
@INPROCEEDINGS{Kanaujia06fastmp:a,
author = {Shobhit Kanaujia and Irma Esmer and Papazian Jeff and Chamberlain Jeff Baxter},
title = {FastMP: A Multi-core Simulation Methodology},
booktitle = {The annual Workshop on Modeling, Benchmarking and Simulation (MOBS},
year = {2006}
}
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Abstract
Current architecture trends focus on designs that exploit thread-level parallelism using multiple cores on chip [15], [16]. With increasing number of cores, the simulation run time increases accordingly with best-case linear scaling. These large turnaround times prohibitively limit the ability to evaluate performance tradeoffs during the design phase. In this paper, we propose a multi-core simulation methodology aimed specifically at addressing runtime scalability. We use SPECrate, a commonly used throughput metric for multi-processor evaluation as our test case, but expect the methodology is applicable to performance simulations for general class of homogeneous multi-threaded workloads that do not share data. The approach is to simulate a subset of cores in detail and use real-time analysis of the detailed cores ’ behavior as the basis for approximating the memory traffic of other cores. We provide a detailed evaluation of FastMP by measuring the simulation speedup and measurement error compared against fully detailed simulation of all cores for core counts of 2, 4 and 8. We show results for every workload in the SPEC CPU 2000 suite. Our methodology introduces reasonable errors and obtains average runtime speedups of 1.9, 3.1 and 5.9 for 2, 4 and 8 core simulations respectively.
Keyphrases
multi-core simulation methodology design phase memory traffic multiple core large turnaround time time increase general class spec cpu core simulation runtime scalability performance simulation performance tradeoff simulation speedup test case best-case linear scaling obtains average runtime speedup current architecture trend methodology introduces reasonable error detailed simulation core count detailed core share data multi-processor evaluation measurement error real-time analysis homogeneous multi-threaded workload exploit thread-level parallelism detailed evaluation
