DMCA
Timing Optimization of Logic Network Using Gate Duplication (1999)
| Venue: | In Proc. Asia and South Pacific Design Automation Conference |
| Citations: | 10 - 3 self |
BibTeX
@INPROCEEDINGS{Chen99timingoptimization,
author = {Chun-hong Chen and Chi-ying Tsui},
title = {Timing Optimization of Logic Network Using Gate Duplication},
booktitle = {In Proc. Asia and South Pacific Design Automation Conference},
year = {1999},
pages = {233--236}
}
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Abstract
We present a timing optimization algorithm based on gate duplication. We first examine the relationship between gate duplication and delay reduction, and then introduce the notion of duplication gain for selecting the good candidate gates to be duplicated. The objective is to obtain the maximum delay reduction with the minimum duplications. The performance of the algorithm is demonstrated with experiments on benchmark circuits. Our approach can also be combined with other technologyindependent timing optimizers (such as speed-up) to achieve further delay improvement. 1 Introduction Timing optimization has been an important goal in logic synthesis. In the technology-independent phase, the internal structure of a Boolean network is restructured to obtain a logically equivalent network with the reduced maximum logic level or reduced longest path delay under a given delay model. In the technologydependent phase, technology mapping for minimum delay improves the circuit timing by selectin...
Keyphrases
logic network using gate duplication gate duplication introduction timing optimization good candidate gate timing optimization algorithm equivalent network duplication gain logic synthesis minimum delay benchmark circuit important goal circuit timing technologydependent phase path delay minimum duplication delay model delay reduction internal structure reduced maximum logic level boolean network technology-independent phase delay improvement maximum delay reduction technology mapping
